Dynamic Power Reduction in Sram
نویسندگان
چکیده
To reduce the dynamic power consumption in SRAM a new design technique is proposed here. The proposed technique is compared with 8T SRAM cell design technique using 0.18 micron technology. Simulation results indicates that the proposed technique provides an improvement of 64% in bitline leakage ,22.64% in write ‘0’ power, 30.68% in write ‘1’ power over 8T SRAM cell design technique.
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